1. Field of the Invention
This invention relates to an apparatus for detecting the capacity of a random access memory (RAM) such as a memory card and, more particularly, to a memory capacity detection apparatus wherein, in a RAM in which a memory space is constituted by 2.sup.N blocks each having a predetermined capacity, a detection code is written at a specific address of the RAM, and an image of the detection code is generated so as to enable the memory capacity of the RAM to be determined.
The invention also relates to an electronic applied measuring device using the memory capacity detection apparatus described above and, more particularly, to an electronic applied measuring device which is capable of detecting the memory capacity of a memory for storing data which is necessary in measuring procedures and/or processes of the measuring equipment.
2. Description of the Related Art
In recent years, memory cards including programmable memories (RAMs) have come to be used in a variety of different fields, and are naturally used for electronic applied measuring devices. The specific application of such a memory card is determined by the card issuer, and hence, there is no need for detecting a storage capacity, i.e., a memory capacity of the memory card at the equipment side.
However, when memory cards are used in a variety of fields, use of a single memory card in all the systems is preferred. The memory capacity of a given memory card, as well as its cost, depends on the storage capacity of the memory chip embedded therein. Therefore, memory cards having different memory capacities are distributed. Therefore, an equipment must detect the memory capacity of a memory card to be used, especially for a read/write access. If the equipment cannot detect the memory capacity of a memory card to be used, important existing data may be broken or new data may not be stored safely.
When data having an address represented by a larger number of bits than that of an address corresponding to an existing memory space is present, data stored in lower blocks is rewritten by an image address.
The way in which an image address is generated will now be explained below.
In order to increase a memory capacity of a programmable RAM, some techniques are employed. One of these techniques is a technique wherein a memory space corresponding to a power of 2 is given as a fundamental unit (2.sup.J bytes, J is a positive integer), and a memory capacity is increased by a step (2.sup.J+N) of 2.sup.N (N=0, 1, 2, . . . ) times the fundamental unit. For example, when a memory having a larger memory capacity than a memory whose fundamental unit corresponds to 2.sup.13 bytes (J=13) is to be provided, a memory capacity is increased like 2.sup.13+1 bytes (N=1), 2.sup.13+2 bytes (N=2), . . .
Virtual blocks are set in all the memory spaces of a RAM having a fundamental unit of 2.sup.J bytes and a total capacity of 2.sup.J+N bytes as shown in the Table below.
______________________________________ Range of Address Number of Virtual Lower Upper Bits of Memory Block Address Address Address Space ______________________________________ First 2.sup.0 2.sup.J J Funda- Block mental unit (2.sup.J) Second 2.sup.J + 1 2.sup.(J+1) J + 1 2.sup.0 Block times of Funda- mental unit Third 2.sup.(J+1) + 1 2.sup.(J+2) J + 2 2.sup.1 Block times of Funda- mental unit (N + 1)th 2.sup.(J+N-1) 2.sup.(J+N) J + N 2.sup.(N-1) Block + 1 times of Funda- mental unit ______________________________________
When an address is expressed in binary notation, the number of bits of an address is increased by one bit toward upper blocks such that an address corresponding to the memory space of a first block is J bits, an address corresponding to the memory space of a second block is (J+1) bits, and so on, as shown in the Table above. Considering an address from the least significant bit to a Kth bit (bits equal to and larger than a (J+1)th bit are ignored, an address equal to that address is present in all the blocks.
When an address larger than an address corresponding to an existing memory space (2.sup.(J+1) bytes), e.g., a nonexisting address ((J+N+Y) bits) such as 2.sup.(J+N+Y) (Y.gtoreq.1), is designated, the upper Y bits of the address are ignored, and an address which is equal to the value of lower bits (J+N), and which corresponds to a memory present in a lower block, is read out. The actually readout address (which differs from the designated address) is called an image address of the designated address.
The present invention aims at detecting a memory capacity by utilizing the feature of generation of an image address, which causes a problem upon use of a RAM.